Date：2019-06-18 Categories：Industry News Hits：445
There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coating, selecting appropriate EMI suppression parts and EMI simulation design. Based on the most basic PCB layout, this paper discusses the function and design skills of PCB stack in controlling EMI radiation.
power bus
The output voltage jump of IC can be accelerated by placing appropriate capacitance near the power pin of IC. However, this is not the end of the problem. Due to the limited frequency response of the capacitor, it is impossible for the capacitor to generate the harmonic power needed to drive the IC output cleanly in the full frequency band. In addition, the transient voltage formed on the power bus will cause voltage drop at both ends of the inductance of the decoupling path. These transient voltages are the main common mode EMI interference sources. How can we solve these problems?
In the case of IC on our circuit board, the power layer around the IC can be regarded as a good high-frequency capacitor, which can collect the energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of a good power layer is small, so the transient signal synthesized by the inductor is also small, thus reducing the common mode EMI.
Of course, the connection between the power supply layer and the IC power supply pin must be as short as possible, because the rising edge of the digital signal is faster and faster. It is better to connect it directly to the pad where the IC power pin is located, which needs to be discussed separately.
In order to control common mode EMI, the power layer must be a well-designed pair of power layers to facilitate decoupling and to have a sufficiently low inductance. One may ask, how good is it? The answer to the question depends on the delamination of the power supply, the material between the layers and the operating frequency (i.e. a function of IC rise time). In general, the spacing of power layers is 6mil, and the interlayer is FR4 material, so the equivalent capacitance per square inch of power layer is about 75pF. Obviously, the smaller the layer spacing, the larger the capacitance.
There are not many devices with a rise time of 100-300ps, but according to the current development rate of IC, the devices with rise time in the range of 100-300ps will occupy a high proportion. For circuits with 100 to 300 PS rise times, 3 mil layer spacing will no longer be suitable for most applications. At that time, it is necessary to adopt the delamination technology with the interlayer spacing less than 1mil and replace the FR4 dielectric material with the material with high dielectric constant. Now, ceramics and potted plastics can meet the design requirements of 100 to 300ps rise time circuits.
Although new materials and methods may be used in the future, the common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing, and FR4 dielectric materials are generally sufficient to handle high-end harmonics and make transient signals low enough, that is, common mode EMI can be reduced very low. In this paper, the design example of PCB layered stacking is given, and the layer spacing is assumed to be 3 to 6 mil.
electromagnetic shielding
From the signal routing point of view, a good layering strategy should be to place all the signal traces in one or more layers, which are next to the power layer or ground plane. For power supply, a good layering strategy should be that the power layer is adjacent to the ground plane, and the distance between the power layer and the ground plane should be as small as possible. This is what we call the "layering" strategy.
power bus
The output voltage jump of IC can be accelerated by placing appropriate capacitance near the power pin of IC. However, this is not the end of the problem. Due to the limited frequency response of the capacitor, it is impossible for the capacitor to generate the harmonic power needed to drive the IC output cleanly in the full frequency band. In addition, the transient voltage formed on the power bus will cause voltage drop at both ends of the inductance of the decoupling path. These transient voltages are the main common mode EMI interference sources. How can we solve these problems?
In the case of IC on our circuit board, the power layer around the IC can be regarded as a good high-frequency capacitor, which can collect the energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of a good power layer is small, so the transient signal synthesized by the inductor is also small, thus reducing the common mode EMI.
Of course, the connection between the power supply layer and the IC power supply pin must be as short as possible, because the rising edge of the digital signal is faster and faster. It is better to connect it directly to the pad where the IC power pin is located, which needs to be discussed separately.
In order to control common mode EMI, the power layer must be a well-designed pair of power layers to facilitate decoupling and to have a sufficiently low inductance. One may ask, how good is it? The answer to the question depends on the delamination of the power supply, the material between the layers and the operating frequency (i.e. a function of IC rise time). In general, the spacing of power layers is 6mil, and the interlayer is FR4 material, so the equivalent capacitance per square inch of power layer is about 75pF. Obviously, the smaller the layer spacing, the larger the capacitance.
There are not many devices with a rise time of 100-300ps, but according to the current development rate of IC, the devices with rise time in the range of 100-300ps will occupy a high proportion. For circuits with 100 to 300 PS rise times, 3 mil layer spacing will no longer be suitable for most applications. At that time, it is necessary to adopt the delamination technology with the interlayer spacing less than 1mil and replace the FR4 dielectric material with the material with high dielectric constant. Now, ceramics and potted plastics can meet the design requirements of 100 to 300ps rise time circuits.
Although new materials and methods may be used in the future, the common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing, and FR4 dielectric materials are generally sufficient to handle high-end harmonics and make transient signals low enough, that is, common mode EMI can be reduced very low. In this paper, the design example of PCB layered stacking is given, and the layer spacing is assumed to be 3 to 6 mil.
electromagnetic shielding
From the signal routing point of view, a good layering strategy should be to place all the signal traces in one or more layers, which are next to the power layer or ground plane. For power supply, a good layering strategy should be that the power layer is adjacent to the ground plane, and the distance between the power layer and the ground plane should be as small as possible. This is what we call the "layering" strategy.
10 ply board
Because of the very thin insulation layer between multi-layer boards, the impedance between 10 or 12 layers of circuit boards is very low. As long as the lamination and stacking are not problematic, excellent signal integrity can be expected. There are many difficulties in manufacturing 12 layer plate according to 62 mil thickness, and there are not many manufacturers who can process 12 layer plate.
Since there is always an insulating layer between the signal layer and the loop layer, it is not the best scheme to allocate the middle six layers to go through the signal line in the 10 layer board design. In addition, it is important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power supply, ground, signal, signal, ground and signal.
This design provides a good path for the signal current and its loop current. The appropriate routing strategy is to route layer 1 in X direction, layer 3 in Y direction, layer 4 in X direction, and so on. Intuitively, the first layer, the first layer and the third layer are a pair of layered combination, the fourth layer and the seventh layer are a pair of layered combination, and the eighth and tenth layer are the last pair of layered combination. When the routing direction needs to be changed, the signal line on the first layer should be changed after passing through the third layer. In fact, it may not always be possible to do so, but as a design concept, we should try to follow it.
Similarly, when the routing direction of the signal changes, the via should be used from layers 8 and 10 or from layer 4 to layer 7. This wiring ensures the tightest coupling between the forward path and the loop of the signal. For example, if the signal is routed on layer 1, and the loop is in layer 2 and only in layer 2, then even if the signal on layer 1 is transferred to layer 3 by "via", the loop is still in layer 2, thus maintaining the characteristics of low inductance, large capacitance and good electromagnetic shielding performance.
What if the actual routing is not like this? For example, the signal line on the first layer passes through the via hole to the tenth layer. At this time, the loop signal has to find the grounding plane from the ninth layer, and the loop current needs to find the nearest grounding via (such as the grounding pin of resistor or capacitor). If you happen to have such vias nearby, you're really lucky. If there is no such near vias available, the inductance will increase, the capacitance will be reduced, and the EMI will certainly increase.
When the signal line must leave the current pair of wiring layers to other wiring layers through vias, grounding vias should be placed near the vias, so that the loop signals can return to the appropriate ground plane smoothly. For layer 4 and layer 7 combination, the signal loop will return from the power layer or ground layer (i.e. layer 5 or layer 6), because the capacitance coupling between the power layer and the ground layer is good and the signal is easy to transmit.
Design of multi power layer
If two power layers of the same voltage source need to output large current, the circuit board should be arranged into two groups of power supply layers and grounding layers. In this case, an insulating layer is placed between each pair of power layers and the ground plane. In this way, we can get two pairs of power busbars with equal impedance to divide the current. If the stacking of power layers causes unequal impedance, the shunt will be uneven, the transient voltage will be much higher, and the EMI will increase sharply.
If there are multiple supply voltages with different values on the circuit board, multiple power layers are required accordingly, and it is important to remember to create separate power layers and ground planes for different power supplies. In both cases, bear in mind the manufacturer's requirements for balanced construction when determining the location of the paired power and ground planes on the circuit board.
summary
Since most of the circuit boards designed by engineers are traditional printed circuit boards with thickness of 62 mil and without blind holes or buried holes, the discussion on delamination and stacking of circuit boards in this paper is limited to this. The delamination scheme recommended in this paper may not be ideal for circuit boards with too large thickness difference. In addition, due to the different processing process of PCB with blind hole or buried hole, the delamination method in this paper is not applicable.
In the design of circuit board, the thickness, the process of via hole and the number of layers of circuit board are not the key to solve the problem. Good layered stacking is the key to ensure the bypass and decoupling of power bus, to minimize the transient voltage on the power layer or ground plane, and to shield the electromagnetic field of signal and power supply. Ideally, there should be an insulating layer between the signal wiring layer and its loop grounding layer, and the smaller the matching layer spacing (or more than one pair), the better. According to these basic concepts and principles, we can design a circuit board that can always meet the design requirements. Now, the rise time of IC is very short and will be shorter. The technology discussed in this paper is essential to solve EMI shielding problem.